1. Field of the Invention
The present invention relates to a linear feedback shift register (LSFR) for use in a pulse signal test circuit, and more specifically, to a linear feedback shift register capable of modifying a generator polynomial f(x) under control of a multiplexor.
2. Description of Related Art
In the prior art, linear feedback shift registers have been widely used in pseudo random pattern generators and in signature analyzers for error detection in data transmission and others. However, all of the conventional linear shift registers has been constructed to have a fixed generator polynomial.
The conventional linear shift registers having a fixed generator polynomial has various limitations in their actual applications. For example, in a build-up self test of digital circuits such as CPU (central processing unit) and ASIC (application specific integrated circuit) on the basis of a "design for testability", it has been a general practice to construct a register called a "build-in logic block observer". This build-in logic block generator has a test pattern generator function and a data compression function called a "parallel signature analyzer". In a self-test mode, either the test pattern generator or the parallel signature analyzer is selected by an external control signal.
Both of the test pattern generator and the parallel signature analyzer are fundamentally constituted of a liner feedback shift register. When the test pattern generator function is selected, the linear feedback shift register constitutes a pseudo random pattern generator which has a fixed generator polynomial (called a "primitive polynomial") and a maximum period corresponding to the number of bits of the linear feedback shift register.
In general, a plurality of build-in logic block observers are provided in a circuit under test, each one of the build-in logic block observers corresponding to each one divided circuit which is a circuit to be measured or tested, and each output terminal of the test pattern generator forming each one virtual input terminal to the divided circuit. Now, assuming that the divided circuit is a combinational circuit, a pattern having a maximum period corresponding to the number of bits of the linear feedback shift register is ideally required. Also, assuming that the number of bits of the linear feedback shift register is "n", the number of generated patterns becomes (2.sup.n -1). This number of generated patterns can be realized if the number of virtual input terminals of the divided circuit, namely, the number of bits of the linear feedback shift register, is small. However, if the number of virtual input terminals of the divided circuit is large, the above number of patterns cannot be realized because of a limited time for test. As a result, it has been required to fulfil a predetermined degree of fault coverage by use of a restricted number of random patterns.
On the other hand, the divided circuit includes a sequential circuit, the divided circuit have to be sequentially supplied with input signals. Accordingly, even if a pattern of the maximum period corresponding to the number of bits of the linear feedback shift register (which pattern is called a "exhaustive pattern") is used, only incomplete result can be obtained. More still, it is difficult to fulfil the predetermined degree of fault coverage by use of the restricted number of random patterns.
As mentioned above, the linear feedback shift register used in the conventional build-in logic block observer has constituted a fixed generator polynomial in a hardware structure, and therefore, can function only as a generator for a fixed pseudo random pattern. As a result, it has been difficult to realize a self-test having a high degree of fault coverage.